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{{Infobox software
| name = Vivado Design Suite
| title = Vivado Design Suite
| logo = لوگو ویوادو.jpg
| latest release date = {{Start date and age|2025|3|12}}<ref name="rel_notes">[https://china.xilinx.com/support/download/index.html/content/xilinx/zh/downloadNav/vivado-design-tools/2024-2.html Vivado Design Suite Release Notes] {{Wayback|url=https://china.xilinx.com/support/download/index.html/content/xilinx/zh/downloadNav/vivado-design-tools/2024-2.html |date=20250421113730 }}, Xilinx</ref>
| genre = [[Electronic design automation|EDA]]
| language = [[英语]]
| size =
| platform =
| operating system = [[Microsoft Windows]], [[Linux]]
| programming language = [[C++]]
| latest preview date =
| latest preview version =
| latest release version = 2024.2.2<ref>[https://docs.amd.com/r/zh-CN/ug973-vivado-release-notes-install-license • Vivado Design Suite User Guide] {{Wayback|url=https://docs.amd.com/r/zh-CN/ug973-vivado-release-notes-install-license |date=20240923142618 }}, Xilinx</ref>
| discontinued =
| released = {{Start date and age|2012|04|df=yes}}<ref name="Xilinx-Inc-Apr-2012-8-K">{{cite web |url=http://edgar.secdatabase.com/846/119312512182086/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Apr 25, 2012 |publisher=secdatabase.com |accessdate=May 6, 2018 |archive-date=2022-03-25 |archive-url=https://web.archive.org/web/20220325020340/http://edgar.secdatabase.com/846/119312512182086/filing-main.htm }}</ref>
| developer = [[Xilinx]]
| author =
| collapsible =
| caption = Xilinx Vivado Design Suite 2014.2 with Block Design panel (center) and project navigation tree (left)
| license = [[共享软件]]
| website = https://www.amd.com/zh-cn/products/software/adaptive-socs-and-fpgas/vivado.html
}}
'''Vivado Design Suite'''（也称为 '''Xilinx Vivado''' 或 '''Vivado'''）是 [[赛灵思|Xilinx]] 开发的用于 [[硬件描述语言|HDL]] 设计的合成和分析的软件套件，具有用于[[单片系统|片上系统]]开发和[[高级综合]]的附加功能。<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20141118-datacenter|title=FPGAs Cool Off the Datacenter, Xilinx Heats Up the Race|first=Kevi|author=Morris|publisher=Electronic Engineering Journal|date=2014-11-18|accessdate=2020-08-30|archive-date=2016-04-12|archive-url=https://web.archive.org/web/20160412035331/http://www.eejournal.com/archives/articles/20141118-datacenter}}</ref><ref name="hls1">{{Cite web|title=Xilinx and its Ecosystem Demonstrate All Programmable and Smarter Vision Solutions at ISE 2015|url=http://www.prnewswire.com/news-releases/xilinx-and-its-ecosystem-demonstrate-all-programmable-and-smarter-vision-solutions-at-ise-2015-300030385.html|date=2015-02-04|access-date=2020-08-30|archive-date=2022-01-29|archive-url=https://web.archive.org/web/20220129103411/https://www.prnewswire.com/news-releases/xilinx-and-its-ecosystem-demonstrate-all-programmable-and-smarter-vision-solutions-at-ise-2015-300030385.html}}</ref><ref>{{Cite news|url=http://www.design-reuse.com/news/31035/xilinx-vivado-design-suite-webpack-edition.html|title=Xilinx Vivado Design Suite Now Available in WebPACK Edition|date=2012-12-19|location=SAN JOSE|publisher=Design & Reuse|accessdate=2020-08-30|archive-date=2020-07-20|archive-url=https://web.archive.org/web/20200720044930/https://www.design-reuse.com/news/31035/xilinx-vivado-design-suite-webpack-edition.html}}</ref>，它取代了之前的 [[Xilinx ISE]]。<ref>{{Cite web|title=Xilinx vs. Altera, Calling the Action in the Greatest Semiconductor Rivalry|url=http://www.eejournal.com/archives/articles/20140225-rivalry/|author=Morris|date=2014-02-25|first=Kevin|publisher=Electronic Engineering Journal|access-date=2020-08-30|archive-date=2017-04-28|archive-url=https://web.archive.org/web/20170428143458/http://www.eejournal.com/archives/articles/20140225-rivalry}}</ref><ref>[http://www.xilinx.com/products/design-tools/vivado.html Vivado Design Suite] {{Wayback|url=http://www.xilinx.com/products/design-tools/vivado.html |date=20220517225509 }}, Xilinx Website</ref><ref>[http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/v2012_2---14_2.html Vivado Design Suite] {{Wayback|url=http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/v2012_2---14_2.html |date=20220201111846 }}, First version released in 2012, Xilinx Downloads</ref>

和较新版本的 [[Xilinx ISE|ISE]] 一样，Vivado 包含了内置的逻辑仿真器 [https://www.xilinx.com/products/design-tools/isim.html ISIM] {{Wayback|url=https://www.xilinx.com/products/design-tools/isim.html |date=20220412055012 }}。<ref>[http://www.xilinx.com/products/design-tools/vivado.html#buy Vivado Features] {{Wayback|url=http://www.xilinx.com/products/design-tools/vivado.html#buy |date=20220517225509 }}, Xilinx</ref>Vivado还引入了高级综合，其工具链可将 C 代码转换为可编程逻辑。<ref name="hls1"/>

Xilinx 用 Vivado Design Suite 替换有15年的寿命的 [[Xilinx ISE|ISE]] 软件，花费了 1000 人·年的工作时间及 2 亿美元。<ref>{{Cite web|title=The road to success is long and hard for eda start ups|url=http://www.newelectronics.co.uk/electronics-technology/the-road-to-success-is-long-and-hard-for-eda-start-ups/58277/|author=Joselyn|date=2013-12-10|first=Louise|publisher=New Electronics|access-date=2020-08-30|archive-date=2020-11-11|archive-url=https://web.archive.org/web/20201111222359/https://www.newelectronics.co.uk/electronics-technology/the-road-to-success-is-long-and-hard-for-eda-start-ups/58277/}}</ref>

== 特性 ==
Vivado 于2012年4月推出，它是一个[[集成开发环境]]（IDE），具有在共享可伸缩数据模型（scalable data model）和公共调试环境（common debug environment）上构建的系统到IC级工具。Vivado 包含用于综合和验证基于 C 的算法 [[IP核|IP 核]]的电子系统级（ESL）设计工具；基于标准的算法和 RTL IP 包以供重用；基于标准的 IP 缝合和所有类型的系统构件的系统集成；以及块和系统的验证。<ref>EDN. "[http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X] {{Wayback|url=http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X |date=20130116054344 }}." Jun 15, 2012. Retrieved Jun 25, 2013.</ref>Vivado 的免费版本 WebPACK Edition 为设计人员提供了有限功能的设计环境。<ref>Clive Maxfield, EE Times. "[http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4403821/WebPACK-edition-of-Xilinx-Vivado-Design-Suite-now-available WebPACK edition of Xilinx Vivado Design Suite now available] {{Wayback|url=http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4403821/WebPACK-edition-of-Xilinx-Vivado-Design-Suite-now-available |date=20130211010306 }}." Dec 20, 2012. Retrieved Jun 25, 2013.</ref>

== 组件 ==
'''Vivado High-Level Synthesis'''（Vivado 高级综合）是可将[[C语言|C]]、[[C++|C ++]] 和 [[SystemC]] 程序可以直接转换以供 Xilinx 器件使用的编译器，用户可无需手动创建RTL。<ref>[http://www.design-reuse.com/news/35626/xilinx-zynq-7000-vivado-design-suite-2014-3.html Xilinx Accelerates Productivity for Zynq-7000 All Programmable SoCs with the Vivado Design Suite 2014.3, SDK, and New UltraFast Embedded Design Methodology Guide] {{Wayback|url=http://www.design-reuse.com/news/35626/xilinx-zynq-7000-vivado-design-suite-2014-3.html |date=20210519015140 }}, SAN JOSE, Oct. 8, 2014, Design & Reuse</ref><ref name="hls2">{{Cite web|title=Vivado Design Suite 2014.1 Increases Productivity with Automation of UltraFast Design Methodology and OpenCL Hardware Acceleration|url=http://www.marketwatch.com/story/vivado-design-suite-20141-increases-productivity-with-automation-of-ultrafast-design-methodology-and-opencl-hardware-acceleration-2014-04-16|date=2014-04-16|publisher=Market Watch|access-date=2020-08-30|archive-date=2017-04-24|archive-url=https://web.archive.org/web/20170424224114/http://www.marketwatch.com/story/vivado-design-suite-20141-increases-productivity-with-automation-of-ultrafast-design-methodology-and-opencl-hardware-acceleration-2014-04-16}}</ref><ref>{{Cite web|title=Free High-Level Synthesis Guide for S/W Engineers|url=http://www.eetimes.com/document.asp?doc_id=1319061|author=Maxfield|date=2013-07-26|first=Clive|publisher=EE Times|access-date=2020-08-30|archive-date=2017-09-08|archive-url=https://web.archive.org/web/20170908085533/http://www.eetimes.com/document.asp?doc_id=1319061}}</ref>Vivado 高级综合支持 C++ 类、模板、函数和运算符重载。<ref name="hls3">{{Cite web|title=How to make slow software run quicker|url=http://www.electronicsweekly.com/news/components/programmable-logic-and-asic/make-slow-software-run-quicker-2014-05/|author=Wilson|date=2014-05-27|first=Richard|publisher=[[Electronics Weekly]]|access-date=2020-08-30|archive-date=2015-09-24|archive-url=https://web.archive.org/web/20150924010654/http://www.electronicsweekly.com/news/components/programmable-logic-and-asic/make-slow-software-run-quicker-2014-05/}}</ref>Vivado 2014.1引入了对将 Xilinx 设备的 [[OpenCL]] 内核自动转换为 IP 核的支持。<ref name="tcl">{{Cite web|title=Viva Vivado!, Xilinx Tunes-Up Tools|url=http://www.eejournal.com/archives/articles/20140506-vivavivado/|author=Morris|date=2014-05-06|first=Kevin|publisher=Electronic Engineering Journal|access-date=2020-08-30|archive-date=2017-04-23|archive-url=https://web.archive.org/web/20170423122149/http://www.eejournal.com/archives/articles/20140506-vivavivado}}</ref>OpenCL 内核是可以在各种 CPU，GPU 和 FPGA 平台上执行的程序。

'''Vivado Simulator'''（Vivado 仿真器）是Vivado设计套件的组件。它是一种编译语言模拟器，支持混合语言、TCL 脚本、加密 IP 核和增强的验证。

'''Vivado IP Integrator'''（Vivado IP 核集成）使工程师可以通过大型 Xilinx IP 库快速集成和配置 IP 核。该集成器还针对使用 Xilinx 的系统生成器（System Generator）和 Vivado 高级综合构建的 [[迈斯沃克|MathWorks]] [[Simulink]] 设计进行了优化。<ref>{{Cite web|title=Xilinx, MathWorks and National Instruments work on high-level FPGA design|url=http://www.electronicsweekly.com/news/design/embedded-systems/xilinx-mathworks-and-national-instruments-work-on-high-level-fpga-design-2013-09/|author=Wilson|date=2013-09-11|first=Richard|publisher=[[Electronics Weekly]]|access-date=2020-08-30|archive-date=2015-09-24|archive-url=https://web.archive.org/web/20150924010718/http://www.electronicsweekly.com/news/design/embedded-systems/xilinx-mathworks-and-national-instruments-work-on-high-level-fpga-design-2013-09/}}</ref>

'''Vivado TCL Store''' 是用于为 Vivado 开发附加组件的脚本系统，可用于添加和修改 Vivado 的功能。<ref name="tcl"/>TCL 即[[Tcl|工具命令语言]]（Tool Command Language），并且是 Vivado 本身所基于的脚本语言。Vivado的所有基础功能都可以通过 TCL 脚本来调用和控制。

== 设备支持 ==
Vivado 支持 Xilinx 的7-系列及所有更加新的设备（UltraScale 和 UltraScale+ 系列）。<ref name="rel_notes"/>若需要使用 Xilinx 的旧设备开发，则需要使用已经停止更新的 [[Xilinx ISE]] 软件。

== 参考文献 ==
{{Reflist|30em}}

== 参见 ==
* [[Xilinx ISE]]
* [[Altera Quartus]]
* [[ModelSim]]

== 外部链接 ==
* {{Official website|https://www.xilinx.com/products/design-tools/vivado.html}}

{{可编程逻辑设备}}

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Xilinx Vivado - 版本历史

imported>Hzy99：​修改“当前版本”

imported>Hzy99：修改“当前版本”