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Verilog-AMS - 版本历史
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'''Verilog-AMS'''是[[Verilog]][[硬件描述语言]]的一个衍生。它包含了[[模拟电路|模拟]]和[[混合訊號積體電路|混合信号]]扩展模块，以实现对于模拟电路和混合信号系统行为的描述。它扩展了Verilog、SystemVerilog等的事件驱动[[电子电路仿真|仿真器]]的回路，通过使用一个连续时间仿真器，可以在模拟域（{{lang|en|analog-domain}}）上求解微分方程。模拟事件可以触发数字行为，反之亦可。<ref>Scheduling semantics are specified in the Verilog/AMS Language Reference Manual, section 8.</ref><br />
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== 参考文献 ==<br />
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== 外部链接 ==<br />
* I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," ''Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems'', pp. 305-308, Available: https://web.archive.org/web/20070927051749/http://www.nsti.org/publ/MSM2000/T31.01.pdf<br />
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=== 一般的资料 ===<br />
* [https://web.archive.org/web/20120723015901/http://www.verilog.org/verilog-ams/ Accellera Verilog Analog Mixed-Signal Group]<br />
* [https://web.archive.org/web/20190611093910/http://www.verilog-ams.com/ verilog-ams.com]<br />
* [http://www.designers-guide.org/VerilogAMS/ The Designer's Guide Community, Verilog-A/MS] {{Wayback|url=http://www.designers-guide.org/VerilogAMS/ |date=20181214194826 }} — Examples of models written in Verilog-AMS]<br />
* [http://www.eda.org/twiki/bin/view.cgi/VerilogAMS EDA.ORG AMS Wiki]{{Wayback|url=http://www.eda.org/twiki/bin/view.cgi/VerilogAMS |date=20110214103703 }} - Issues, future development, SystemVerilog integration<br />
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=== 开源资料 ===<br />
* [http://ovams.sourceforge.net/ OpenVAMS, a Open-Source VerilogAMS-1.3 Parser with internal VPI-like representation] {{Wayback|url=http://ovams.sourceforge.net/ |date=20210701163310 }}<br />
* [http://www.v-ms.com/ V2000 project - Verilog-AMS parser & elaborator] {{Wayback|url=http://www.v-ms.com/ |date=20220411070158 }}<br />
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[[Category:硬件描述语言|V]]</div>
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