编辑“︁Intel 8080”︁（章节）

=== 指令集 ===
{| class="wikitable" style="text-align:center"
! colspan="8" |操作码
! colspan="2" |操作数
! rowspan="2" |助记符
! rowspan="2" |周期数
! rowspan="2" |描述
|-
!7
!6
!5
!4
!3
!2
!1
!0
!b2
!b3
|-
|0
|0
|0
|0
|0
|0
|0
|0
|&mdash;
|&mdash;
| align="left" |NOP
|4
| align="left" |No operation
|-
|0
|0
| colspan="2" |RP
|0
|0
|0
|1
|''datlo''
|''dathi''
| align="left" |LXI ''rp,data''
|10
| align="left" |RP ← ''data''
|-
|0
|0
| colspan="2" |RP
|0
|0
|1
|0
|&mdash;
|&mdash;
| align="left" |STAX ''rp''
|7
| align="left" |(RP) ← A [BC or DE only]
|-
|0
|0
| colspan="2" |RP
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |INX ''rp''
|5
| align="left" |RP ← RP + 1
|-
|0
|0
| colspan="3" |DDD
|1
|0
|0
|&mdash;
|&mdash;
| align="left" |INR ''ddd''
|5/10
| align="left" |DDD ← DDD + 1
|-
|0
|0
| colspan="3" |DDD
|1
|0
|1
|&mdash;
|&mdash;
| align="left" |DCR ''ddd''
|5/10
| align="left" |DDD ← DDD - 1
|-
|0
|0
| colspan="3" |DDD
|1
|1
|0
|''data''
|&mdash;
| align="left" |MVI ''ddd,data''
|7/10
| align="left" |DDD ← data
|-
|0
|0
| colspan="2" |RP
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |DAD ''rp''
|10
| align="left" |HL ← HL + RP
|-
|0
|0
| colspan="2" |RP
|1
|0
|1
|0
|&mdash;
|&mdash;
| align="left" |LDAX ''rp''
|7
| align="left" |A ← (RP) [BC or DE only]
|-
|0
|0
| colspan="2" |RP
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |DCX ''rp''
|5
| align="left" |RP ← RP - 1
|-
|0
|0
|0
|0
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RLC
|4
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
|0
|0
|0
|0
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RRC
|4
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
|0
|0
|0
|1
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RAL
|4
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
|-
|0
|0
|0
|1
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RAR
|4
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
|-
|0
|0
|1
|0
|0
|0
|1
|0
|''addlo''
|''addhi''
| align="left" |SHLD ''add''
|16
| align="left" |(add) ← HL
|-
|0
|0
|1
|0
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |DAA
|4
| align="left" |If A<sub>0-3</sub> > 9 OR AC = 1 then A ← A + 6;
then if A<sub>4-7</sub> > 9 OR Cy = 1 then A ← A + 0x60
|-
|0
|0
|1
|0
|1
|0
|1
|0
|''addlo''
|''addhi''
| align="left" |LHLD ''add''
|16
| align="left" |HL ← (add)
|-
|0
|0
|1
|0
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |CMA
|4
| align="left" |A ← ¬A
|-
|0
|0
|1
|1
|0
|0
|1
|0
|''addlo''
|''addhi''
| align="left" |STA ''add''
|13
| align="left" |(add) ← A
|-
|0
|0
|1
|1
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |STC
|4
| align="left" |Cy ← 1
|-
|0
|0
|1
|1
|1
|0
|1
|0
|''addlo''
|''addhi''
| align="left" |LDA ''add''
|13
| align="left" |A ← (add)
|-
|0
|0
|1
|1
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |CMC
|4
| align="left" |Cy ← ¬Cy
|-
|0
|1
| colspan="3" |DDD
| colspan="3" |SSS
|&mdash;
|&mdash;
| align="left" |MOV ''ddd,sss''
|5/7
| align="left" |DDD ← SSS
|-
|0
|1
|1
|1
|0
|1
|1
|0
|&mdash;
|&mdash;
| align="left" |HLT
|7
| align="left" |Halt
|-
|1
|0
| colspan="3" |ALU
| colspan="3" |SSS
|&mdash;
|&mdash;
| align="left" |ADD ADC SUB SBB ANA XRA ORA CMP ''sss''
|4/7
| align="left" |A ← A [ALU operation] SSS
|-
|1
|1
| colspan="3" |CC
|0
|0
|0
|&mdash;
|&mdash;
| align="left" |Rcc
|5/11
| align="left" |If cc true, PC ← (SP), SP ← SP + 2
|-
|1
|1
| colspan="2" |RP
|0
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |POP ''rp''
|10
| align="left" |RP ← (SP), SP ← SP + 2
|-
|1
|1
| colspan="3" |CC
|0
|1
|0
|''addlo''
|''addhi''
| align="left" |Jcc ''add''
|10
| align="left" |If cc true, PC ← add
|-
|1
|1
|0
|0
|0
|0
|1
|1
|''addlo''
|''addhi''
| align="left" |JMP ''add''
|10
| align="left" |PC ← add
|-
|1
|1
| colspan="3" |CC
|1
|0
|0
|''addlo''
|''addhi''
| align="left" |Ccc ''add''
|11/17
| align="left" |If cc true, SP ← SP - 2, (SP) ← PC, PC ← add
|-
|1
|1
| colspan="2" |RP
|0
|1
|0
|1
|&mdash;
|&mdash;
| align="left" |PUSH ''rp''
|11
| align="left" |SP ← SP - 2, (SP) ← RP
|-
|1
|1
| colspan="3" |ALU
|1
|1
|0
|''data''
|&mdash;
| align="left" |ADI ACI SUI SBI ANI XRI ORI CPI ''data''
|7
| align="left" |A ← A [ALU operation] data
|-
|1
|1
| colspan="3" |N
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RST ''n''
|11
| align="left" |SP ← SP - 2, (SP) ← PC, PC ← N x 8
|-
|1
|1
|0
|0
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |RET
|10
| align="left" |PC ← (SP), SP ← SP + 2
|-
|1
|1
|0
|0
|1
|1
|0
|1
|''addlo''
|''addhi''
| align="left" |CALL ''add''
|17
| align="left" |SP ← SP - 2, (SP) ← PC, PC ← add
|-
|1
|1
|0
|1
|0
|0
|1
|1
|''port''
|&mdash;
| align="left" |OUT ''port''
|10
| align="left" |Port ← A
|-
|1
|1
|0
|1
|1
|0
|1
|1
|''port''
|&mdash;
| align="left" |IN ''port''
|10
| align="left" |A ← Port
|-
|1
|1
|1
|0
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |XTHL
|18
| align="left" |HL ↔ (SP)
|-
|1
|1
|1
|0
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |PCHL
|5
| align="left" |PC ← HL
|-
|1
|1
|1
|0
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |XCHG
|4
| align="left" |HL ↔ DE
|-
|1
|1
|1
|1
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |DI
|4
| align="left" |Disable interrupts
|-
|1
|1
|1
|1
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |SPHL
|5
| align="left" |SP ← HL
|-
|1
|1
|1
|1
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EI
|4
| align="left" |Enable interrupts
|-
!7
!6
!5
!4
!3
!2
!1
!0
!b2
!b3
!助记符
!周期数
!描述
|-
! colspan="13" |
|-
! colspan="5" |SSS DDD
!2
!1
!0
! colspan="2" |CC
!ALU
!RP
!
|-
| colspan="5" |B
|0
|0
|0
| colspan="2" |NZ
| align="left" |ADD ADI (A ← A + arg)
|BC
|-
| colspan="5" |C
|0
|0
|1
| colspan="2" |Z
| align="left" |ADC ACI (A ← A + arg + Cy)
|DE
|-
| colspan="5" |D
|0
|1
|0
| colspan="2" |NC
| align="left" |SUB SUI (A ← A - arg)
|HL
|-
| colspan="5" |E
|0
|1
|1
| colspan="2" |C
| align="left" |SBB SBI (A ← A - arg - Cy)
|SP or PSW
|-
| colspan="5" |H
|1
|0
|0
| colspan="2" |PO
| align="left" |ANA ANI (A ← A ∧ arg)
|-
| colspan="5" |L
|1
|0
|1
| colspan="2" |PE
| align="left" |XRA XRI (A ← A ⊻ arg)
|-
| colspan="5" |M
|1
|1
|0
| colspan="2" |P
| align="left" |ORA ORI (A ← A ∨ arg)
|-
| colspan="5" |A
|1
|1
|1
| colspan="2" |N
| align="left" |CMP CPI (A - arg)
|-
! colspan="5" |SSS DDD
!2
!1
!0
! colspan="2" |CC
!ALU
! colspan="2" |
|}